Clock Stretching And Accommodation Of Additional System Status And Control Signals

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I2C (inter-integrated circuit bus) was developed in the early 1980s1. In the early 1990s, Intel created an enhanced version of I2C called SMBus2 (system management bus) for power and thermal management systems in server and PC applications. In the early 2000s, SMBus2 was chosen as the physical interface for PMBus, an open specification for managing modular power systems, opening yet another market for I2C /SMBus products. Today, the venerable I2C bus continues to grow in popularity because of its low cost and overhead, strong industry support and relatively efficient communication protocol. As a result, I2C has been adopted in many new end applications.

In many of these applications, I2C/SMBus interfaces require galvanic isolation for safety or ground loop elimination. For example, Power over Ethernet (PoE) applications typically use an I2C interface for communication between the PoE power sourcing device (PSE) and the earth-ground-referenced system controller. Galvanic isolation is required both by standard and also as a practical matter to prevent ground loops in Ethernet connected equipment. The physical interface consists of two wires: serial data (SDA) and serial clock (SCL). These wires are connected to open collector drivers that serve as both inputs and outputs. At first glance, it appears that SDA and SCL can be isolated simply by placing two unidirectional isolators in parallel and in opposite directions. However, this technique creates feedback that latches the bus line low when a logic low is asserted by either master or slave. This problem can be remedied by adding anti-latch circuits3 but results in a larger, more expensive solution.

Recent breakthroughs in silicon RF isolation technology enable both the isolation and anti-latch functions to be integrated in single packages, such as the Silicon Laboratories Si8400 and Si8405 I2C bidirectional isolators4. These products offer a single-chip, anti-latch solution to the problem of isolating I2C /SMBus applications and require no external components except the I2C /SMBus pull-up resistors. In addition, the devices provide isolation to a maximum of 2.5 kVACRMS, support clock stretching, and operate to a maximum bus speed of 2 Mbps.

Two other important system level design considerations are clock stretching and accommodation of additional system status and control signals that typically require isolation.
It is clear that the data line (SDA) needs to be bidirectional as this line contains data that can be either from the host to the slave or from the slave to the host. It is also common practice for the slave device to hold the clock line (SCL) low during the "acknowledge" (ACK) period while it is retrieving data for the master. For "clock stretching" to work in a particular I2C design, an I2C isolator that is also a bidirectional channel on the SCL line must be used. Without bidirectional isolation on the SCL signal, the designer must ensure that all I2C slaves can operate with the same bus clock rate and timing characteristics as the master. This places additional design and validation burdens on the system developer.

The Si8400 is bidirectional for both SCL and SDA. Besides SCL and SDA signal isolation, many designs also require additional system status and control signals, such as resets and interrupt lines, to be isolated. The use of monolithic I2C isolators with additional unidirectional channels allows the system designer to simplify timing challenges in a design. Instead of being forced to isolate additional status and control channels in multiple isolator or opto-coupler packages (which results in significant part-to-part timing variations), monolithic I2C isolators with extra unidirectional channels exhibit timing characteristics that track very closely across process, voltage and temperature variations. The Si8405 has two additional unidirectional channels that are useful for isolating reset and interrupt signals. I2C design does not have to be a mystery. By considering each of these design tips and choosing an isolator appropriate to the demands, designers can easily implement I2C in their products.

Silicon Labs - SLIC and Clock Generator

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